sales@gozuk.comFailures of power supplies
Aug 21, 2013 22:30 PM
Symptom: FET failure
Cause: Inadequate FET contact to heatsink (Mechanical)
Symptom: FET failure
Cause: unbalanced bridge, saturating magnetics, caused by asymmetrical layout and current sensing. (PCB Layout and control circuit)
Symptom: FET failure
Cause: Reverse recovery of antiparallel diode due to noise injected from current transformer location and layout.(Circuit arrangement and layout.)
Symptom: FET failure
Cause: Saturating magnetics during startup due to control chip having minimum on-time. (Control chip misbehavior)
Symptom: FET failure
Cause: High frequency operation due to noise clock, layout around IC. (PCB Layout)
Symptom: FET failure
Cause: No current limit implemented. (Circuit protection issue.)
symptom: FET failure
Cause: saturating magnetics due to core overheating cause by proximity losses. (Magnetics)
Symptom: HV diode failure
Cause: inadequate spacing in PCB internal layers (Layout design)
Symptom: FET failure
Cause: Marginal manufacturer of FETs. (I won't say who.)
Symptom: FET failure
Cause: Circuit not snubbed enough, forced recovery of antiparallel diode. (Magnetics, circuit design)
The point is it usually looks like the FET is the problem. But these are pretty rugged devices if you treat them nicely.
Personally I think mainly caused by limited risk management, lack of attention to detail, not enough time or a poor test regime. When you are experienced in designing power supplies and systems you understand which aspects have the highest risk and how the customer is likely to use it, because of this you can mitigate most of the risks by upfront tests, detailed prototype testing and targeted system tests. I remember a few things from engineers I have worked with in the past, one that didn't want to cycle the AC mains to his PFC design just in case it failed and another that thought it acceptable to fit a thermal fuse to protect an LV output as the current limit rolled out to 800% under short circuit conditions.
I think the key is to consider all the possible different problems and effects at every stage of the development, it is very important to make sure you fully understand the application and have a fully detailed specification even if you have to write it yourself.
I must admit I have probably suffered most from not checking PCB's in enough detail, only to have to sort out the problem at the prototype stage which takes longer!
Cause: Inadequate FET contact to heatsink (Mechanical)
Symptom: FET failure
Cause: unbalanced bridge, saturating magnetics, caused by asymmetrical layout and current sensing. (PCB Layout and control circuit)
Symptom: FET failure
Cause: Reverse recovery of antiparallel diode due to noise injected from current transformer location and layout.(Circuit arrangement and layout.)
Symptom: FET failure
Cause: Saturating magnetics during startup due to control chip having minimum on-time. (Control chip misbehavior)
Symptom: FET failure
Cause: High frequency operation due to noise clock, layout around IC. (PCB Layout)
Symptom: FET failure
Cause: No current limit implemented. (Circuit protection issue.)
symptom: FET failure
Cause: saturating magnetics due to core overheating cause by proximity losses. (Magnetics)
Symptom: HV diode failure
Cause: inadequate spacing in PCB internal layers (Layout design)
Symptom: FET failure
Cause: Marginal manufacturer of FETs. (I won't say who.)
Symptom: FET failure
Cause: Circuit not snubbed enough, forced recovery of antiparallel diode. (Magnetics, circuit design)
The point is it usually looks like the FET is the problem. But these are pretty rugged devices if you treat them nicely.
Personally I think mainly caused by limited risk management, lack of attention to detail, not enough time or a poor test regime. When you are experienced in designing power supplies and systems you understand which aspects have the highest risk and how the customer is likely to use it, because of this you can mitigate most of the risks by upfront tests, detailed prototype testing and targeted system tests. I remember a few things from engineers I have worked with in the past, one that didn't want to cycle the AC mains to his PFC design just in case it failed and another that thought it acceptable to fit a thermal fuse to protect an LV output as the current limit rolled out to 800% under short circuit conditions.
I think the key is to consider all the possible different problems and effects at every stage of the development, it is very important to make sure you fully understand the application and have a fully detailed specification even if you have to write it yourself.
I must admit I have probably suffered most from not checking PCB's in enough detail, only to have to sort out the problem at the prototype stage which takes longer!
