How to optimize the power dissipated in a switching MOSFET transistor?

Optimization often deals with minimizing or maximizing certain system variables. If you specify what your objectives are, the members of the group might offer better "how-to" suggestions.

If you are concerned mainly about reducing Power dissipation then, you must operate the MOSFET in the Linear region ( I-V curve : high current @ low voltages) and also make sure you don't drive MOSFET into Saturation region.

If the MOSFET is to be used as a switch, only turning on and off, there are three regions of operation to consider when calculating power losses in the device: (1) the off-state, (2) the transition (active region) state and (3) the on-state. Each of the states can be modeled using piece-wise linear circuit models from which v-i power loss equations can be derived. In the off-state, the device needs to behave as a perfect insulator but leakage current combined with high voltage produce power loss. In the on-state, the device needs to behave as a perfect conductor but high current combined with a small voltage drop combined to produce power loss. In the transition state turning on or off, the device makes a transition from low-to-high current and high-to-low voltage and it is in this state that the device will produce the greatest power loss. Efficient designs all require that the transition state be as fast as possible but this is not an easy objective due to circuit inductance and charging capacitance of the device. The fundamental laws of physics prevail: current can't change instantly in an inductor and voltage can't change instantly in a capacitor. Thus, the optimization centers around how to get through the transition state as quickly as possible given the circuit conditions and this leads to the development of gate drivers for controlling charge and snubbers for controlling inductive current effects. Obviously, this gets too complex to discuss here but it is a start.

Thank you Mr. Jim for a comprehensive answer. But, when you talk of Gate drivers and Snubber circuits, would it be "High side"gate driver with Totem pole arrangement which would be the ideal design and does using just a resistor in series would help as a snubber circuit. Please give your suggestions.

Best regards,
Rakesh Venkatesha Murthy
Cell: 301.302.6423