In this age of off-the-shelf SMPSs with internally compensated feedback loops on large PCBs, one can actually create unanticipated problems with inter-loop oscillations. The PFC/SMPS combination is the most common example, but the PFC stage has a such low bandwidth that it appears to be more of a battery. On a large PCB, it is a little more complicated where higher bandwidth SMPSs are cascaded. Buying off-the-shelf solutions can present some surprises.

There are all kinds of opportunities for trouble with these systems.

The PFC can actually have trouble with the input source impedance, you can sometimes see oscillations in the fast current loop of the PFC.

The slow voltage loop on the output means that the Z out is dominated by the capacitor impedance. Since it is designed to take 120Hz ripple it is usually large enough to present low output impedance to the next stage.

However, follow that with an LC stage using MLCs and high impedance peaks can occur and interact with the subsequent switcher. MLCs are great, but they do provide undamped filters.

That can continue down the line if you have point of load converters following on.

Good points, Ray.

In this age of "ceramic stable" SMPS ICs and the much higher switching frequencies (ie higher control loop bandwidths) as off-the-shelf, simpler offerings, there can be unforeseen system stability issues. Many of the internally switched ICs also have internally compensated feedback loops and are current mode controlled. This means that the filter poles move around depending upon their load impedances (resistive or complex).
There are many additional influences including: output capacitor type, trace/plane impedances, ESRs,, local input capacitances, etc. Back to the topic, with the moving poles and the fixed compensation of each stage can move the phase of cascaded SMPSs to similar frequencies to one another, thus creating a net phase which can be interactive. Under-damped or sustained system responses can be initiated by a step load change and/or a changing inductive load impedance. In short, test your system for all expected operating conditions.

This is an issue that I have seen before. Engineers going away and designing their power supplies in isolation of each other. All power supplies stable (When tested separately). System unstable when connected together. Result? Engineers arguing over the cause!

Bit of a nightmare to try and de-bug. The end result was due to some of the filter issues. The use of film caps meant there there were some singificant resoant peaks the design which interfered in the feedback loops of the downstream controller.Quick re-design of some the filter stages (Damping networks applied) and all was happy again but still bit a of a headache to de-bug but all good fun though.....

Luke, I like your passion. I had once collaborated on a book in the late 1990's, for a SPMS appendix,.by Paul Duran about high level modeling (now out of print) and about how the feedback compensation can lead to series loop instability. I have one copy given to me by the author. I will need to dig it out and relay some of the findings. High-level modeling is OK because it treats the control functions as black boxes, but well defined. Stay tuned.